Invention Grant
- Patent Title: CMOS-based thermopile with reduced thermal conductance
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Application No.: US15350694Application Date: 2016-11-14
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Publication No.: US09853086B2Publication Date: 2017-12-26
- Inventor: Henry Litzmann Edwards , Toan Tran , Jeffrey R. Debord , Ashesh Parikh , Bradley David Sucher
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Michael A. Davis, Jr.; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L27/16 ; H01L35/04 ; H01L21/265 ; H01L21/8238 ; H01L27/06 ; H01L29/34 ; H01L35/32 ; H01L35/34 ; H01L27/092

Abstract:
In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.
Public/Granted literature
- US20170062518A1 CMOS-BASED THERMOPILE WITH REDUCED THERMAL CONDUCTANCE Public/Granted day:2017-03-02
Information query
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