Invention Grant
- Patent Title: Method of manufacturing a trench FET having a merged gate dielectric
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Application No.: US15186133Application Date: 2016-06-17
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Publication No.: US09853142B2Publication Date: 2017-12-26
- Inventor: Ling Ma
- Applicant: Infineon Technologies Americas Corp.
- Applicant Address: US CA El Segundo
- Assignee: Infineon Technologies Americas Corp.
- Current Assignee: Infineon Technologies Americas Corp.
- Current Assignee Address: US CA El Segundo
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/306 ; H01L29/66 ; H01L29/40 ; H01L29/78 ; H01L29/423 ; H01L29/08 ; H01L29/10

Abstract:
In one implementation, a method for fabricating a trench FET includes providing a semiconductor substrate including a drain region and a drift zone over the drain region, forming a plurality of depletion trenches over the drain region, each of the plurality of depletion trenches having a depletion trench dielectric and a depletion electrode, and forming a respective bordering gate trench alongside each of the plurality of depletion trenches, each bordering gate trench having a gate electrode and a gate dielectric.
Public/Granted literature
- US20160293754A1 Method of Manufacturing a Trench FET Having a Merged Gate Dielectric Public/Granted day:2016-10-06
Information query
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