Chip arrangement and method for manufacturing a chip arrangement

Invention Grant

US09856136B2 Chip arrangement and method for manufacturing a chip arrangement 有权

Patent Title: Chip arrangement and method for manufacturing a chip arrangement
Application No.: US13910133

Application Date: 2013-06-05
Publication No.: US09856136B2

Publication Date: 2018-01-02
Inventor: Thorsten Meyer , Gerald Ofner , Christian Mueller , Reinhard Mahnkopf , Christian Geissler , Andreas Augustin
Applicant: Intel Mobile Communications GmbH
Applicant Address: DE Neubiberg
Assignee: Intel Deutschland GmbH
Current Assignee: Intel Deutschland GmbH
Current Assignee Address: DE Neubiberg
Agency: Viering, Jentschura & Partner mbB
Main IPC: H01L29/84
IPC: H01L29/84 ; B81B7/00 ; B81C1/00 ; H01L23/00

Abstract:

A chip arrangement may include: a mold compound; and a microelectromechanical systems device at least partially embedded in the mold compound.

Public/Granted literature

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IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L29/00	专门适用于整流、放大、振荡或切换，并具有至少一个电位跃变势垒或表面势垒的半导体器件；具有至少一个电位跃变势垒或表面势垒，例如PN结耗尽层或载流子集结层的电容器或电阻器；半导体本体或其电极的零部件（H01L31/00至H01L47/00，H01L51/05优先；除半导体或其电极之外的零部件入H01L23/00；由在一个共用衬底内或其上形成的多个固态组件组成的器件入H01L27/00）
H01L29/66	.按半导体器件的类型区分的
H01L29/84	..通过所施加的机械力，如压力的变化可控的（H01L29/96优先）