Invention Grant
- Patent Title: Dynamic window to improve NAND endurance
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Application No.: US15076963Application Date: 2016-03-22
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Publication No.: US09857992B2Publication Date: 2018-01-02
- Inventor: Kiran Pangal , Ravi J. Kumar
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alpine Technology Law Group LLC
- Main IPC: G11C29/02
- IPC: G11C29/02 ; G11C29/50 ; G11C29/10 ; G11C29/04 ; G06F3/06 ; G06F11/10 ; G06F11/20 ; G11C11/56 ; G11C16/14 ; G11C16/26 ; G11C16/34 ; G11C29/52 ; G11C16/00

Abstract:
Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20160357458A1 DYNAMIC WINDOW TO IMPROVE NAND ENDURANCE Public/Granted day:2016-12-08
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