Invention Grant
- Patent Title: Low overhead paged memory runtime protection
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Application No.: US15051213Application Date: 2016-02-23
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Publication No.: US09858202B2Publication Date: 2018-01-02
- Inventor: Ravi L. Sahita , Xiaoning Li , Manohar R. Castelino
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alpine Technology Law Group LLC
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/109 ; G06F12/1009 ; G06F9/455 ; G06F12/14 ; G06F12/02
Abstract:
Methods and apparatus relating to low overhead paged memory runtime protection are described. In an embodiment, permission information for guest physical mapping are received prior to utilization of paged memory by an Operating System (OS) based on the guest physical mapping. The permission information is provided through an Extended Page Table (EPT). Other embodiments are also described.
Public/Granted literature
- US20160170902A1 LOW OVERHEAD PAGED MEMORY RUNTIME PROTECTION Public/Granted day:2016-06-16
Information query
