Invention Grant
- Patent Title: Systems and methods for cache management for universal serial bus systems
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Application No.: US15343997Application Date: 2016-11-04
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Publication No.: US09858205B2Publication Date: 2018-01-02
- Inventor: Xingzhi Wen , Yu Hong , Hefei Zhu , Qunzhao Tian , Jeanne Q. Cai , Shaori Guo
- Applicant: Marvell World Trade Ltd.
- Applicant Address: BB St. Michael
- Assignee: MARVELL WORLD TRADE LTD.
- Current Assignee: MARVELL WORLD TRADE LTD.
- Current Assignee Address: BB St. Michael
- Main IPC: G06F12/12
- IPC: G06F12/12 ; G06F12/123 ; G06F12/0862 ; G06F12/0868 ; G06F12/0875 ; G06F12/121

Abstract:
A system includes a cache and a cache-management component. The cache includes a plurality of cache lines that correspond to a plurality of device endpoints. The cache-management component is configured to receive a transfer request block (TRB) for data transfer involving a device endpoint. In response to a determination that the cache both (i) does not include a cache line assigned to the device endpoint and (ii) does not include an empty cache line, the cache-management component assigns, to the device endpoint, a last cache line that includes a most recently received TRB in the cache, and stores the received TRB to the last cache line.
Public/Granted literature
- US20170052904A1 Systems and Methods for Cache Management for Universal Serial Bus Systems Public/Granted day:2017-02-23
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