Invention Grant
- Patent Title: Variable change memory and the writing method of the same
-
Application No.: US15261771Application Date: 2016-09-09
-
Publication No.: US09858973B2Publication Date: 2018-01-02
- Inventor: Shintaro Sakai , Masahiko Nakayama , Katsuyuki Fujita , Hiromi Noro
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Holtz, Holtz & Volek PC
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/16 ; G11C13/00 ; H01L27/22 ; H01L43/08 ; H01L43/10

Abstract:
According to one embodiment, a variable change memory includes a bit line, a word line, a memory cell array, a resonance line, a clock generator, and a write driver. The bit line extends in a first direction. The word line extends in a second direction. The memory cell array includes blocks. The each block includes memory cells including a transistor and a variable resistive element. The resonance line connects to a bit line. The clock generator is arranged in the memory cell array and applies a voltage to the resonance line. The write driver supplies a write current to the bit line. The voltage oscillates at the predetermined period and the write current are supplied to the bit line.
Public/Granted literature
- US20160379697A1 VARIABLE CHANGE MEMORY AND THE WRITING METHOD OF THE SAME Public/Granted day:2016-12-29
Information query