Invention Grant
- Patent Title: Semiconductor device and method for writing thereto
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Application No.: US15038747Application Date: 2014-08-26
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Publication No.: US09859016B2Publication Date: 2018-01-02
- Inventor: Sumio Katoh , Naoki Ueda
- Applicant: Sharp Kabushiki Kaisha
- Applicant Address: JP Sakai
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Sakai
- Agency: Keating & Bennett, LLP
- Priority: JP2013-243052 20131125
- International Application: PCT/JP2014/072293 WO 20140826
- International Announcement: WO2015/075985 WO 20150528
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C17/18 ; G11C13/00 ; G11C17/16 ; G11C19/28 ; H01L27/105 ; H01L27/112 ; H01L29/24 ; H01L29/786 ; G02F1/1345 ; G02F1/1368

Abstract:
A semiconductor device (1001) includes: a memory cell; and a writing control circuit (107), wherein the memory cell includes a memory transistor (10A) which has an active layer (7A), the active layer (7A) including a metal oxide, the memory transistor (10A) is a transistor which is capable of being irreversibly changed from a semiconductor state where a drain current Ids depends on a gate-source voltage Vgs to a resistor state where the drain current Ids does not depend on the gate-source voltage Vgs, and the writing control circuit (107) is configured to control voltages applied to a drain electrode, a source electrode and a gate electrode such that Vgs≧Vds+Vth is satisfied where Vth is a threshold voltage of the memory transistor (10A) and Vds is a drain-source voltage of the memory transistor (10A), whereby writing in the memory transistor (10A) is performed.
Public/Granted literature
- US20160379719A1 SEMICONDUCTOR DEVICE AND METHOD FOR WRITING THERETO Public/Granted day:2016-12-29
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