Invention Grant
- Patent Title: Delta-sigma modulator with delta-sigma truncator and associated method for reducing leakage errors of delta-sigma modulator
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Application No.: US15647253Application Date: 2017-07-11
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Publication No.: US09859914B1Publication Date: 2018-01-02
- Inventor: Chan-Hsiang Weng , Tien-Yu Lo
- Applicant: MEDIATEK INC.
- Applicant Address: TW Hsin-Chu
- Assignee: MEDIATEK INC.
- Current Assignee: MEDIATEK INC.
- Current Assignee Address: TW Hsin-Chu
- Agency: Winston Hsu
- Main IPC: H03M3/00
- IPC: H03M3/00 ; H03M1/12 ; H03M1/00

Abstract:
A delta-sigma modulator includes a receiving circuit, a loop filter module, a quantizer, a delta-sigma truncator, a digital filter module, and an output circuit. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter module is arranged for filtering the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a first digital signal according to the filtered summation signal. The delta-sigma truncator is arranged for truncating the first digital signal to generate a second digital signal. The digital filter module is arranged for filtering the first digital signal and the second digital signal to generate a filtered first digital signal and a filtered second digital signal, respectively. The output circuit is arranged for generating an output signal according to the filtered first digital signal and the filtered second digital signal.
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