Techniques described herein are generally related to data transfer in multi-core processor devices. A core of a multi-core processor device may be configured to receive a request for a data block, which may be stored in a private cache of the core. The data block in the private cache may be evaluated by a coherence module of the core to determine when the data block is in a ready state. A program slice associated with the data block may be identified by the coherence module when the data block is determined to be in an unavailable state and the identified program slice may be executed by the core to update the data block from the unavailable state to the ready state. The data block may be sent to an interconnect network in response to the received request when the stored data block is determined to be in the ready state.