Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power

Invention Grant

US09865316B2 Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power 有权

Patent Title: Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power
Application No.: US15003444

Application Date: 2016-01-21
Publication No.: US09865316B2

Publication Date: 2018-01-09
Inventor: Sharad Kumar Gupta , Mukund Narasimhan , Veerabhadra Rao Boda
Applicant: QUALCOMM Incorporated
Applicant Address: US CA San Diego
Assignee: QUALCOMM Incorporated
Current Assignee: QUALCOMM Incorporated
Current Assignee Address: US CA San Diego
Agency: Haynes and Boone, LLP
Main IPC: G11C7/00
IPC: G11C7/00 ; G11C7/22 ; G11C11/419 ; G11C11/418 ; G11C7/12 ; G11C8/08 ; G11C8/10 ; G11C8/18

Abstract:

A memory is provided in which the word line assertion during a write operation is delayed until the discharge of a dummy bit line is detected.

Public/Granted literature

Information query

Espacenet

IPC分类:

G	物理
G11	信息存储
G11C	静态存储器（半导体存储器件入H01L，如H01L27/108-H01L27/11597）
G11C7/00	数字存储器信息的写入或读出装置（G11C5/00优先；用于采用半导体器件的存储器的辅助电路入G11C11/4063，G11C11/413，G11C11/4193）