Invention Grant
- Patent Title: Method for manufacturing isolation structure
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Application No.: US15236173Application Date: 2016-08-12
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Publication No.: US09865496B2Publication Date: 2018-01-09
- Inventor: Eun-Jeong Kim , Jin-Yul Lee , Han-Sang Song , Su-Ho Kim
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T Group LLP
- Priority: KR10-2015-0184820 20151223
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/02

Abstract:
A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.
Public/Granted literature
- US20170186642A1 ISOLATION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME Public/Granted day:2017-06-29
Information query
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