Invention Grant
- Patent Title: Device and methods for high-K and metal gate slacks
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Application No.: US14975055Application Date: 2015-12-18
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Publication No.: US09865510B2Publication Date: 2018-01-09
- Inventor: Po-Nien Chen , Bao-Ru Young , Harry-Hak-Lay Chuang , Jin-Aun Ng , Ming Zhu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/78 ; H01L27/06 ; H01L29/51 ; H01L21/28 ; H01L49/02 ; H01L29/06 ; H01L29/49

Abstract:
A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.
Public/Granted literature
- US20160190018A1 DEVICE AND METHODS FOR HIGH-K AND METAL GATE SLACKS Public/Granted day:2016-06-30
Information query
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