Invention Grant
- Patent Title: Alignment in the packaging of integrated circuits
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Application No.: US15143957Application Date: 2016-05-02
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Publication No.: US09865574B2Publication Date: 2018-01-09
- Inventor: Kuei-Wei Huang , Chih-Wei Lin , Wei-Hung Lin , Ming-Da Cheng , Chung-Shi Liu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L25/10
- IPC: H01L25/10 ; H01L23/31 ; H01L23/498 ; H01L23/544 ; H01L25/00 ; H01L23/00
Abstract:
A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package.
Public/Granted literature
- US20160247790A1 Alignment in the Packaging of Integrated Circuits Public/Granted day:2016-08-25
Information query
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