Invention Grant
- Patent Title: Process for fabrication of superconducting vias for electrical connection to groundplane in cryogenic detectors
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Application No.: US15281371Application Date: 2016-09-30
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Publication No.: US09865795B1Publication Date: 2018-01-09
- Inventor: Kevin L. Denis
- Applicant: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
- Applicant Address: US DC Washington
- Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
- Current Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
- Current Assignee Address: US DC Washington
- Agent Christopher O. Edwards; Bryan A. Geurts; Mark P. Dvorscak
- Main IPC: H01L39/24
- IPC: H01L39/24 ; H01L21/308 ; H01L39/12 ; H01L21/768 ; H01L21/3065 ; H01L21/18 ; H01L21/027 ; H01L23/532 ; H01L23/522
Abstract:
Disclosed are systems, methods, and non-transitory computer-readable storage media for fabrication of silicon on insulator (SOI) wafers with a superconductive via for electrical connection to a groundplane. Fabrication of the SOI wafer with a superconductive via can involve depositing a superconducting groundplane onto a substrate with the superconducting groundplane having an oxidizing layer and a non-oxidizing layer. A layer of monocrystalline silicon can be bonded to the superconducting groundplane and a photoresist layer can be applied to the layer of monocrystalline silicon and the SOI wafer can be etched with the oxygen rich etching plasma, resulting in a monocrystalline silicon top layer with a via that exposes the superconducting groundplane. Then, the fabrication can involve depositing a superconducting surface layer to cover the via.
Information query
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