Invention Grant
- Patent Title: Method for forming resistive memory cell having a spacer region under an electrolyte region and a top electrode
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Application No.: US14952559Application Date: 2015-11-25
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Publication No.: US09865813B2Publication Date: 2018-01-09
- Inventor: Paul Fest
- Applicant: Microchip Technology Incorporated
- Applicant Address: US AZ Chandler
- Assignee: MICROCHIP TECHNOLOGY INCORPORATED
- Current Assignee: MICROCHIP TECHNOLOGY INCORPORATED
- Current Assignee Address: US AZ Chandler
- Agency: Slayden Grubert Beard PLLC
- Main IPC: H01L45/00
- IPC: H01L45/00 ; H01L27/24

Abstract:
A method of forming a resistive memory cell, e.g., CBRAM or ReRAM, includes forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region. An electrically insulating mini-spacer region is formed adjacent the bottom electrode, and an electrolyte region and top electrode are formed over the bottom electrode and mini-spacer element(s) to define a memory element. The memory element defines a conductive filament/vacancy chain path from the bottom electrode pointed tip region to the top electrode via the electrolyte region. The mini-spacer elements decreases the effective area, or “confinement zone,” for the conductive filament/vacancy chain path, which may improve the device characteristics, and may provide an improvement over techniques that rely on enhanced electric field forces.
Public/Granted literature
- US20160079527A1 Resistive Memory Cell Having A Spacer Region For Reduced Conductive Path Area / Enhanced Electric Field Public/Granted day:2016-03-17
Information query
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