A clock recovery circuit includes an oscillator to generate a clock signal. The oscillator varies a frequency of the clock signal as a function of a control signal. The clock recovery circuit has a phase tracking control loop to determine the phase error between the reference signal and the clock signal, and vary the control signal as a function of the phase error. The phase tracking control loop has a linear region for phase errors in the range between −π and +π, thereby creating a cycle slippage event when the phase error exceed said range. The clock recovery circuit includes a cycle-slippage detector which determines whether the phase error reaches or approaches +π or −π. In case the phase error reaches or approaches +π or −π, the cycle-slippage detector acts on the control signal in an effort to avoid that said phase tracking control loop leaves said linear region.