Semiconductor memory device
Abstract:
A semiconductor memory device includes a block including a plurality of string units, each including a plurality of memory cells electrically connected in series, a bad string register in which information indicating which of the string units is a bad string is stored, and a control circuit. The control circuit controls an erase operation on the memory cells, the erase operation including a first erase operation followed by a first verify operation and as needed a subsequent erase operation followed by a subsequent verify operation. During the erase operation, the control circuit skips a verify operation for a string unit if the information in the bad string register indicates the string unit is a bad string.
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