Invention Grant
- Patent Title: Schemes for forming barrier layers for copper in interconnect structures
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Application No.: US14841346Application Date: 2015-08-31
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Publication No.: US09881871B2Publication Date: 2018-01-30
- Inventor: Chen-Hua Yu , Hai-Ching Chen , Tien-I Bao
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L23/532 ; H01L21/768 ; H01L21/322 ; H01L23/528

Abstract:
A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.
Public/Granted literature
- US20150371953A1 Schemes for Forming Barrier Layers for Copper in Interconnect Structures Public/Granted day:2015-12-24
Information query
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