Invention Grant
- Patent Title: Apparatus and method for integrated circuit forensics
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Application No.: US14996554Application Date: 2016-01-15
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Publication No.: US09885745B2Publication Date: 2018-02-06
- Inventor: Brett J Hamilton
- Applicant: The United States of America as represented by the Secretary of the Navy
- Applicant Address: US DC Washington
- Assignee: The United States of America as represented by the Secretary of the Navy
- Current Assignee: The United States of America as represented by the Secretary of the Navy
- Current Assignee Address: US DC Washington
- Agent Christopher A. Monsey
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R1/07 ; G06F11/22 ; G06N3/02 ; G01R31/00

Abstract:
A test system including an embodiment having a sensor array adapted to test one or more devices under test in learning modes as well as evaluation modes. An exemplary test system can collect a variety of test data as a part of a machine learning system associated with known-good samples. Data collected by the machine learning system can be used to calculate probabilities that devices under test in an evaluation mode meet a condition of interest based on multiple testing and sensor modalities. Learning phases or modes can be switched on before, during, or after evaluation mode sequencing to improve or adjust machine learning system capabilities to determine probabilities associated with different types of conditions of interest. Multiple permutations of probabilities can collectively be used to determine an overall probability of a condition of interest which has a variety of attributes.
Public/Granted literature
- US20160131699A1 APPARATUS AND METHOD FOR INTEGRATED CIRCUIT FORENSICS Public/Granted day:2016-05-12
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