Invention Grant
- Patent Title: Integrated circuit with self-verification function, verification method and method for generating a BIST signature adjustment code
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Application No.: US14753032Application Date: 2015-06-29
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Publication No.: US09885754B2Publication Date: 2018-02-06
- Inventor: Chi-Shun Weng , Chun-Yi Kuo
- Applicant: Realtek Semiconductor Corp.
- Applicant Address: TW HsinChu
- Assignee: Realtek Semiconductor Corp.
- Current Assignee: Realtek Semiconductor Corp.
- Current Assignee Address: TW HsinChu
- Agent Winston Hsu
- Priority: TW103123374A 20140707
- Main IPC: G01R29/00
- IPC: G01R29/00 ; G01R31/3193 ; G01R31/3187

Abstract:
An integrated circuit includes a Built-In Self-Test (BIST) circuit, a predetermined signature pattern and a Read Only Memory (ROM), wherein the predetermined signature pattern is stored in the integrated circuit. The ROM stores at least effective information and a BIST signature adjustment code, the BIST signature adjustment code is irrelevant to any functional information stored in the ROM; wherein the BIST circuit is used to test content stored in the ROM to generate a signature pattern, and compare the signature pattern with the predetermined signature pattern to judge if the content stored in the ROM has error.
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