The present invention discloses a replica bit-line circuit, comprising a replica unit, the 1st inverter, the 2nd inverter, the 3rd inverter, the 4th inverter, the 5th inverter, the 6th inverter, the 7th inverter, the 8th inverter, the 9th inverter, the 1st NAND gate, the 2nd NAND gate, the 3rd NAND gate, the 1st NOR gate, the 2nd NOR gate and the 1st PMOS tube; the 2nd NOR gate is provided with the 1st input terminal, the 2nd input terminal, a set terminal and an output terminal; advantages of the present invention are stated as follows: It can inhibit feedback oscillation incurred by replica bit-line and replica wordline signal to obtain accurate wordline control signal; it can save switching power consumption of memory array by 53.7% under the power voltage of 1.2V.