Invention Grant
- Patent Title: Memory system and method for error correction of memory
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Application No.: US15059102Application Date: 2016-03-02
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Publication No.: US09886340B2Publication Date: 2018-02-06
- Inventor: Jung Ho Ahn , Namsung Kim
- Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION , WISCONSIN ALUMNI RESEARCH FOUNDATION
- Applicant Address: KR Seoul US WI Madison
- Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION,WISCONSIN ALUMNI RESEARCH FOUNDATION
- Current Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION,WISCONSIN ALUMNI RESEARCH FOUNDATION
- Current Assignee Address: KR Seoul US WI Madison
- Agency: Korus Patent, LLC
- Agent Seong Il Jeong
- Priority: KR10-2015-0138269 20150930
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F3/06 ; H03M13/29 ; H03M13/19

Abstract:
A memory system and a method for the error correction of memory are disclosed herein. The method for the error correction of memory is performed by a memory system including a plurality of memory chips. The method for the error correction of memory may include reading, by a first ECC engine unit included in each of a plurality of memory chips, a chunk including a plurality of data bursts, first parity bits, and position bits from each of the plurality of memory chips; extracting, by the first ECC engine unit, a single data burst having an error from the plurality of data bursts using the position bits; and performing, by the first ECC engine unit, first error correction using the first parity bit corresponding to the extracted error data burst.
Public/Granted literature
- US20170091025A1 MEMORY SYSTEM AND METHOD FOR ERROR CORRECTION OF MEMORY Public/Granted day:2017-03-30
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