A data transfer device performing data transfer at a high speed if a descriptor chain cannot be entirely transferred by a single activation. In a DMA control device, when a transfer activation signal is asserted, a descriptor information control part sequentially reads descriptor information from a descriptor information storage part. When the count of pieces of descriptor information that have been read becomes equal to a transferable frame count, a backward skip control part outputs a backward skip instruction. When the backward skip instruction is outputted, a descriptor information control part skips reading remaining descriptor information.