- Patent Title: Verification of circuit structures including sub-structure variants
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Application No.: US14540021Application Date: 2014-11-12
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Publication No.: US09886753B2Publication Date: 2018-02-06
- Inventor: Mahantesh Narwade , Namit Gupta , Kaushik De , Rajarshi Mukherjee , Suman Nandan , Subhamoy Pal
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: HIPLegal LLP
- Agent Judith Szepesi
- Priority: EP13192540 20131112
- Main IPC: G06T7/00
- IPC: G06T7/00 ; G06F17/50 ; G06K9/48
Abstract:
A method for controlling the functional output of a verification tool upon receipt of a circuit description comprises searching for a predetermined base pattern in the circuit description. The method further comprises searching for predetermined sub-patterns that are assigned to the base pattern, in the circuit description. The method further comprises the validation of each found sub-pattern based on a predetermined rule to minimize the set of reported errors that based on verification of the circuit description.
Public/Granted literature
- US20150131894A1 VERIFICATION OF CIRCUIT STRUCTURES INCLUDING SUB-STRUCTURE VARIANTS Public/Granted day:2015-05-14
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