Invention Grant
- Patent Title: Semiconductor device manufacturing method
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Application No.: US15448552Application Date: 2017-03-02
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Publication No.: US09887093B1Publication Date: 2018-02-06
- Inventor: Mitsuhiro Omura
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: Patterson & Sheridan, LLP
- Priority: JP2016-185879 20160923
- Main IPC: H01L21/308
- IPC: H01L21/308 ; H01L21/027 ; H01L21/02

Abstract:
A semiconductor device manufacturing method includes forming a first resist and a second resist on a stacked body that includes a plurality of first films and a plurality of second films, the second resist facing one or more side surfaces of the first resist; forming a third film in a slit between the first resist and the second resist, the third film covering the side surfaces of the first resist and defining exposed surfaces of the first resist not covered by the third film; performing a first etch of the stacked body from an upper surface using the first resist, the second resist, and the third film as a mask; selectively etching the one or more exposed surfaces of the first resist and the second resist; and performing a second etch of the stacked body from the upper surface using the first resist and the third film as a mask.
Information query
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