Invention Grant
- Patent Title: Semiconductor chip tray
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Application No.: US14830213Application Date: 2015-08-19
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Publication No.: US09887113B2Publication Date: 2018-02-06
- Inventor: Koji Akimoto , Hisao Nakamura , Tsutomu Fukaya
- Applicant: Synaptics Japan GK
- Applicant Address: JP Tokyo
- Assignee: Synaptics Japan GK
- Current Assignee: Synaptics Japan GK
- Current Assignee Address: JP Tokyo
- Agency: Patterson + Sheridan, LLP
- Priority: JP2014-183216 20140909
- Main IPC: H01L21/673
- IPC: H01L21/673 ; B65D1/36

Abstract:
A semiconductor chip tray is provided that includes a support plate, a first protruding portion, a second protruding portion and a recess. The first protruding portion forms a housing space for a semiconductor chip by being provided on a top surface of the support plate. The second protruding portion is provided on a bottom surface of the support plate, and is fitted to an outer periphery of the first protruding portion of another semiconductor chip tray when the tray is stacked so as to overlap the other tray. The recess is provided on the bottom surface of the support plate. The recess faces a part of the first protruding portion of another chip tray when the tray is stacked so as to overlap the other tray. The recess is formed extending up to an outside of the first protruding portion from the housing space formed by the first protruding portion.
Public/Granted literature
- US20160071752A1 SEMICONDUCTOR CHIP TRAY Public/Granted day:2016-03-10
Information query
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