Invention Grant
- Patent Title: Method and structure for interconnection
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Application No.: US15276456Application Date: 2016-09-26
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Publication No.: US09887128B2Publication Date: 2018-02-06
- Inventor: Hsiang-Wei Lin
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/528 ; H01L21/311 ; H01L23/532 ; H01L21/67 ; H01L21/764

Abstract:
The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes forming a first low-k dielectric layer over a substrate; forming a first and second metal features in the first low-k dielectric layer; forming a first trench in the first low-k dielectric layer, the first trench spanning between the first and second metal features; performing a ultraviolet (UV) treatment to sidewalls of the first low-k dielectric layer in the first trench; forming a first etch stop layer in the first trench; and depositing a second low-k dielectric layer on the first etch stop layer, thereby forming an air gap in the first trench.
Public/Granted literature
- US20170186683A1 Method and Structure for Interconnection Public/Granted day:2017-06-29
Information query
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