Invention Grant
- Patent Title: Molding structure for wafer level package
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Application No.: US14225218Application Date: 2014-03-25
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Publication No.: US09887162B2Publication Date: 2018-02-06
- Inventor: Chen-Hua Yu , Chung-Shi Liu , Chih-Fan Huang , Hui-Min Huang , Wei-Hung Lin , Ming-Da Cheng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/31 ; H01L21/56 ; H01L23/00 ; H01L25/10 ; H01L23/29

Abstract:
A method in which microelectronic devices are attached to a substrate surface, wherein spaces interpose neighboring ones of the microelectronic devices. Each microelectronic device has an outermost surface that is substantially parallel to the substrate surface. The substrate is closed in a transfer molding cavity of a transfer molding apparatus such that an internal surface of the transfer molding cavity contacts a substantial portion of each of the outermost surfaces of the microelectronic devices. A molding compound is subsequently injected into the transfer molding cavity, including into the spaces between ones of the plurality of microelectronic devices.
Public/Granted literature
- US20150171055A1 Molding Structure for Wafer Level Package Public/Granted day:2015-06-18
Information query
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