Invention Grant
- Patent Title: Method of fabricating memory array having divided apart bit lines and partially divided bit line selector switches
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Application No.: US15430888Application Date: 2017-02-13
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Publication No.: US09887240B2Publication Date: 2018-02-06
- Inventor: Seiji Shimabukuro , Teruyuki Mine , Hiroyuki Ogawa , Naoki Takeguchi
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Plano
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Plano
- Agency: Vierra Magen Marcus LLP
- Main IPC: G11C13/00
- IPC: G11C13/00 ; H01L27/24 ; H01L45/00

Abstract:
A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.
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