- Patent Title: Semiconductor device and semiconductor device manufacturing method
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Application No.: US15068534Application Date: 2016-03-11
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Publication No.: US09887260B2Publication Date: 2018-02-06
- Inventor: Yasushi Niimura , Toshiaki Sakata , Shunji Takenoiri
- Applicant: FUJI ELECTRIC CO., LTD.
- Applicant Address: JP Kawasaki-Shi
- Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee Address: JP Kawasaki-Shi
- Agency: Rabin & Berdo, P.C.
- Priority: JP2015-076124 20150402
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/266

Abstract:
A first parallel pn layer in which first n-type regions and first p-type regions are disposed in a plan view layout of stripes in an element active portion. A second parallel pn layer has a plan view layout of stripes oriented in the same direction as that of the stripes of the first parallel pn layer in a breakdown voltage structure portion. Corner portions of the first parallel pn layer has a plan view shape where stepped regions formed by shortening the length of the first n-type and p-type regions in steps are disposed in a stepwise arrangement. The stepped regions continue with a second parallel pn layer via an intermediate region lower in average impurity concentration than the first parallel pn layer.
Public/Granted literature
- US20160293693A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD Public/Granted day:2016-10-06
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