Invention Grant
- Patent Title: Method of reducing the heights of source-drain sidewall spacers of FinFETs through etching
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Application No.: US15398576Application Date: 2017-01-04
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Publication No.: US09887275B2Publication Date: 2018-02-06
- Inventor: Jam-Wem Lee , Tsung-Che Tsai , Yi-Feng Chang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L29/66 ; H01L29/78 ; H01L29/06 ; H01L29/417 ; H01L29/49 ; H01L21/02 ; H01L21/311 ; H01L21/762 ; H01L21/768

Abstract:
A method of forming an integrated circuit device includes forming a gate stack covering a middle portion of a semiconductor fin, forming a gate spacer layer over the gate stack and the semiconductor fin, and patterning the gate spacer layer. The resulting spacers include a gate spacer on a sidewall of the gate stack, and a fin spacer on a sidewall of an end portion of the semiconductor fin. The fin spacer is then etched. When the etching is finished, a height of the fin spacer is smaller than about a half of the height of the semiconductor fin.
Public/Granted literature
- US20170117390A1 Method of Reducing the Heights of Source-Drain Sidewall Spacers of FinFETs Through Etching Public/Granted day:2017-04-27
Information query
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