Invention Grant
- Patent Title: Semiconductor layered structure, method for producing semiconductor layered structure, and method for producing semiconductor device
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Application No.: US15114001Application Date: 2015-01-19
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Publication No.: US09887310B2Publication Date: 2018-02-06
- Inventor: Katsushi Akita , Kei Fujii , Takashi Kyono , Koji Nishizuka , Kaoru Shibata
- Applicant: Sumitomo Electric Industries, Ltd.
- Applicant Address: JP Osaka-shi
- Assignee: Sumitomo Electric Industries, Ltd.
- Current Assignee: Sumitomo Electric Industries, Ltd.
- Current Assignee Address: JP Osaka-shi
- Agency: Venable LLP
- Agent Michael A. Sartori; Miguel A. Lopez
- Priority: JP2014-020199 20140205
- International Application: PCT/JP2015/051173 WO 20150119
- International Announcement: WO2015/118926 WO 20150813
- Main IPC: H01L31/109
- IPC: H01L31/109 ; H01L31/02 ; H01L21/18 ; H01L21/02 ; H01L29/06 ; C30B29/40 ; H01L31/0304 ; H01L31/0352 ; H01L31/105 ; H01L31/0224 ; H01L31/0392 ; H01L31/18

Abstract:
A semiconductor layered structure includes a substrate formed of a III-V compound semiconductor, a buffer layer disposed on and in contact with the substrate and formed of a III-V compound semiconductor, and a quantum well layer disposed on and in contact with the buffer layer and including a plurality of component layers formed of III-V compound semiconductors. The substrate has a diameter of 55 mm or more. At least one of the component layers is formed of a mixed crystal of three or more elements. When the compound semiconductor forming the substrate has a lattice constant d1, the compound semiconductor forming the buffer layer has a lattice constant d2, and the compound semiconductors forming the quantum well layer have an average lattice constant d3, (d2−d1)/d1 is −3×10−3 or more and 3×10−3 or less, and (d3−d1)/d1 is −3×10−3 or more and 3×10−3 or less.
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Information query
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