A silicon-on-sapphire chip with minimal thermal strain preload is provided. The chip includes a sapphire substrate having a first-sapphire surface and an opposing second-sapphire surface; and a silicon layer overlaying the first-sapphire surface. The silicon layer is formed by: creating a plurality of buried cavities in a plane within tens of microns from a first-silicon surface of a silicon wafer; laser fusing the first-silicon surface to the first-sapphire surface at room temperature to attach the silicon wafer to a sapphire wafer; and cleaving the silicon wafer along the plane including the plurality of buried cavities. A silicon-wafer layer is formed from the silicon material between the first-silicon surface and the plane of the plurality of buried cavities. The silicon-wafer layer and the sapphire wafer form a silicon-on-sapphire wafer. The silicon-on-sapphire chip is formed by dicing the silicon-on-sapphire wafer.