Invention Grant
- Patent Title: Secure low voltage testing
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Application No.: US14502406Application Date: 2014-09-30
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Publication No.: US09891277B2Publication Date: 2018-02-13
- Inventor: Joel R. Knight , James B. Eifert , Stefano Pietri , Steven K. Watkins
- Applicant: FREESCALE SEMICONDUCTOR, INC.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R31/317

Abstract:
An integrated circuit includes a normal voltage detector configured to detect a normal voltage at which the integrated circuit being fully functional. A first voltage detector detects a first voltage that is less than the normal voltage. A second voltage detector detects a second voltage that is less than the first voltage. A reset module is coupled to a supply voltage, the normal voltage detector, the first voltage detector, and the second voltage detector. The reset module includes test logic to, when the supply voltage rises to the first voltage from the second voltage, perform a pass/fail test when the integrated circuit is in a pass/fail test mode, and perform a power up reset when the integrated circuit in not in the pass/fail test mode.
Public/Granted literature
- US20160091561A1 SECURE LOW VOLTAGE TESTING Public/Granted day:2016-03-31
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