A pseudo-dual-port (PDP) memory system includes a memory array, timing and control logic, and multiplexer-latch (MUX-latch). The MUX-latch comprises integrated address selection logic and latching logic, such that the combination multiplexes and latches an address in a single change in response to a state change in the read select or write select signals. The multiplexing and latching defines a single operation or state change in the MUX-latch. Since the multiplexing delay and the latching delay for a read operation are coincident with each other rather than being incurred one after the other, memory read operations are fast.