Invention Grant
- Patent Title: Method of manufacturing stacked nanowire MOS transistor
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Application No.: US14688788Application Date: 2015-04-16
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Publication No.: US09892912B2Publication Date: 2018-02-13
- Inventor: Huaxiang Yin , Changliang Qin , Zuozhen Fu , Xiaolong Ma , Dapeng Chen
- Applicant: Institute of Microelectronics, Chinese Academy of Sciences
- Applicant Address: CN Beijing
- Assignee: Institute of Microelectronics, Chinese Academy of Sciences
- Current Assignee: Institute of Microelectronics, Chinese Academy of Sciences
- Current Assignee Address: CN Beijing
- Agency: Knobbe Martens Olson & Bear LLP
- Priority: CN201210392511 20121016
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/02 ; H01L29/00 ; H01L29/775 ; H01L29/06 ; H01L29/423 ; H01L29/786 ; H01L21/8234

Abstract:
Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.
Public/Granted literature
- US20150228480A1 METHOD OF MANUFACTURING STACKED NANOWIRE MOS TRANSISTOR Public/Granted day:2015-08-13
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