Invention Grant
- Patent Title: Lithography using multilayer spacer for reduced spacer footing
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Application No.: US14878798Application Date: 2015-10-08
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Publication No.: US09892933B2Publication Date: 2018-02-13
- Inventor: Chao-Hsien Peng , Hsiang-Huan Lee , Shau-Lin Shue
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/3065 ; H01L21/321 ; H01L21/3105 ; H01L21/3213 ; H01L21/02 ; H01L21/027 ; H01L21/033
Abstract:
A method embodiment for patterning a semiconductor device includes forming a plurality of mandrels over a substrate, and forming a multilayer spacer layer over the plurality of mandrels. The multilayer spacer layer is formed by conformably depositing a spacer layer over the plurality of mandrels and treating the spacer layer with plasma. The plurality of mandrels is exposed by etching a top portion of the multilayer spacer layer, thereby forming a multilayer spacer.
Public/Granted literature
- US20160027658A1 Lithography using Multilayer Spacer for Reduced Spacer Footing Public/Granted day:2016-01-28
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