Invention Grant
- Patent Title: Interconnect structure and method of forming the same
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Application No.: US15213173Application Date: 2016-07-18
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Publication No.: US09892960B2Publication Date: 2018-02-13
- Inventor: Jeng-Shiou Chen , Chih-Yuan Ting , Jyu-Horng Shieh , Minghsing Tsai
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/768 ; H01L23/532 ; H01L23/522 ; H01L23/528

Abstract:
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.
Public/Granted literature
- US20160329237A1 Interconnect Structure and Method of Forming the Same Public/Granted day:2016-11-10
Information query
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