Invention Grant
- Patent Title: Forming a CMOS with dual strained channels
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Application No.: US15288124Application Date: 2016-10-07
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Publication No.: US09892978B2Publication Date: 2018-02-13
- Inventor: Kangguo Cheng , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent L. Jeffrey Kelly
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L21/02 ; H01L21/033 ; H01L29/78 ; H01L21/84 ; H01L27/12

Abstract:
The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and a tensile strained layer on the same wafer. A lower epitaxial layer may be formed adjacent to a tensile strained layer. An upper epitaxial layer may be formed over a portion of the lower epitaxial layer. Thermal oxidation may convert the upper epitaxial layer to an upper oxide layer, and thermal condensation may causes a portion of the lower epitaxial layer to become a compressive strained layer. The upper oxide layer and a remaining portion of the lower epitaxial layer may be removed, leaving the tensile strained layer and the compressive strained layer.
Public/Granted literature
- US20170098583A1 FORMING A CMOS WITH DUAL STRAINED CHANNELS Public/Granted day:2017-04-06
Information query
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