Invention Grant
- Patent Title: Integrated circuits protected by substrates with cavities, and methods of manufacture
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Application No.: US15265148Application Date: 2016-09-14
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Publication No.: US09899281B2Publication Date: 2018-02-20
- Inventor: Hong Shen , Charles G. Woychik , Arkalgud R. Sitaram
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: INVENSAS CORPORATION
- Current Assignee: INVENSAS CORPORATION
- Current Assignee Address: US CA San Jose
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/055 ; H01L23/31 ; H01L21/56 ; H01L21/288 ; H01L21/768 ; H01L25/065 ; H01L25/00 ; H01L23/04 ; H01L23/14 ; H01L23/367 ; H01L23/00 ; H01L23/48 ; H01L23/538 ; H01L21/48 ; H01L23/10

Abstract:
Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.
Public/Granted literature
- US20170040237A1 INTEGRATED CIRCUITS PROTECTED BY SUBSTRATES WITH CAVITIES, AND METHODS OF MANUFACTURE Public/Granted day:2017-02-09
Information query
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