Invention Grant
- Patent Title: Three dimensional integrated circuit electrostatic discharge protection and prevention test interface
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Application No.: US14975951Application Date: 2015-12-21
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Publication No.: US09900970B2Publication Date: 2018-02-20
- Inventor: Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01H47/00
- IPC: H01H47/00 ; H05F3/02 ; H02H9/04 ; G01R1/073 ; G01R1/36 ; H05K1/11 ; H05K1/18

Abstract:
The present disclosure provides a system and method for providing electrostatic discharge protection. A probe card assembly is provided which is electrically connected to a plurality of input/output channels. The probe card assembly can be contacted with a secondary assembly having an interposer electrically connected to one or more wafers each wafer having a device under test. Voltage can be forced on ones of the plural input/output channels of the probe card assembly to slowly dissipate charges resident on the wafer to thereby provide electrostatic discharge protection. A socket assembly adaptable to accept a 3DIC package is also provided, the assembly having a loadboard assembly electrically connected to a plurality of input/output channels. Once the 3DIC package is placed within the socket assembly, voltage is forced on ones of the input/output channels to slowly dissipate charges resident on the 3DIC package to thereby provide electrostatic discharge protection.
Public/Granted literature
- US20160113099A1 THREE DIMENSIONAL INTEGRATED CIRCUIT ELECTROSTATIC DISCHARGE PROTECTION AND PREVENTION TEST INTERFACE Public/Granted day:2016-04-21
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