Invention Grant
- Patent Title: Memory system having a plurality of writing modes
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Application No.: US15391184Application Date: 2016-12-27
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Publication No.: US09910597B2Publication Date: 2018-03-06
- Inventor: Hiroshi Yao , Shinichi Kanno , Kazuhiro Fukutomi
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-214221 20100924
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F3/06 ; G06F12/02

Abstract:
According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
Public/Granted literature
- US20170109050A1 MEMORY SYSTEM HAVING A PLURALITY OF WRITING MODES Public/Granted day:2017-04-20
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