An arithmetic processing apparatus has OS arithmetic processing unit executing instruction of OS, general-purpose arithmetic processing units each executing an instruction other than OS, a shared cache unit including a shared cache memory, a cache control unit and a request selection circuit which selects a memory access request from the arithmetic processing units, and a data buffer temporarily storing data of the memory access request, and a memory access control unit controlling a memory access to a main memory. The shared cache unit has a memory access band control register to which either one or both of a first set value, which includes an entry criterion for the request selection circuit to enter the memory access request from OS arithmetic processing unit, and a second set value which sets a capacity of a storage area in the data buffer for storing the data are set.