Invention Grant
- Patent Title: Vector-matrix multiplications involving negative values
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Application No.: US15201040Application Date: 2016-07-01
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Publication No.: US09910827B2Publication Date: 2018-03-06
- Inventor: Naveen Muralimanohar , Ben Feinberg , Ali Shafiee-Ardestani
- Applicant: Hewlett Packard Enterprise Development LP
- Applicant Address: US TX Houston
- Assignee: Hewlett Packard Enterprise Development LP
- Current Assignee: Hewlett Packard Enterprise Development LP
- Current Assignee Address: US TX Houston
- Agency: Hewlett Packard Enterprise Patent Department
- Main IPC: G06G7/16
- IPC: G06G7/16 ; G06F17/16 ; H03M1/12 ; H03M1/66

Abstract:
Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.
Public/Granted literature
- US20180004708A1 VECTOR-MATRIX MULTIPLICATIONS INVOLVING NEGATIVE VALUES Public/Granted day:2018-01-04
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