This application discloses a computing system to implement a design verification tool and simulate a circuit design with a test bench. The computing system can correlate transactions captured during simulation of a circuit design to distributed states for multiple components in the circuit design. The computing system can identify at least a portion of the distributed states for the multiple components correspond to system level coverage events. The computing system can generate a graphical presentation to illustrate the portion of the distributed states for the multiple components in the circuit design that correspond to system level coverage events.