In some embodiments, a memory device includes a memory bank, a global data line, a first tri-state unit, a latch, a second tri-state unit and a pre-charge unit. The first tri-state unit is configured between the memory bank and the global data line. The latch is configured to provide a state signal based on a data signal from the memory bank. The second tri-state unit is configured between the global data line and the latch. The pre-charge unit pre-charges the global data line to a first intermediate level or a second intermediate level depending on the state signal during the global data line is caused to be electrically isolated from the memory bank by the first tri-state unit and electrically isolated from the latch by the second tri-state unit.