Invention Grant
- Patent Title: Methods for forming a semiconductor arrangement with multiple-height fins and substrate trenches
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Application No.: US15368786Application Date: 2016-12-05
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Publication No.: US09911658B2Publication Date: 2018-03-06
- Inventor: Tsung-Yu Chiang , Kuang-Hsin Chen , Hsin-Lung Chao , Chen Chu-Hsuan
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
- Current Assignee Address: TW
- Agency: Cooper Legal Group, LLC
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/762 ; H01L29/78 ; H01L29/10 ; H01L21/308 ; H01L29/66 ; H01L27/088 ; H01L23/544

Abstract:
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to form a first etched region over a planar region of a semiconductor arrangement. The first etched region exposes a planar structure, such as an alignment mark used for alignment during semiconductor fabrication. The etch sequence forms a second etched region over a semiconductor fin region of the semiconductor arrangement. In an embodiment, the etch sequence forms a first trench, a first fin nub and a first pillar in the semiconductor fin region, where the first trench is formed in a semiconductor substrate of the semiconductor fin region. A multi-depth STI structure is formed over at least one of the first trench, the first fin nub, or the first pillar.
Public/Granted literature
- US20170084494A1 MULTI-DEPTH ETCHING IN SEMICONDUCTOR ARRANGEMENT Public/Granted day:2017-03-23
Information query
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