Integrated circuits with spacer chamfering and methods of spacer chamfering
Abstract:
Semiconductor devices and methods for forming the devices with spacer chamfering. One method includes, for instance: obtaining a wafer with at least one source, at least one drain, and at least one fin; forming at least one sacrificial gate with at least one barrier layer; forming a first set of spacers adjacent to the at least one sacrificial gate; forming at least one second set of spacers adjacent to the first set of spacers; and etching to remove a portion of the first set of spacers above the at least one barrier layer to form a widened opening. An intermediate semiconductor device is also disclosed.
Information query
Patent Agency Ranking
0/0