Invention Grant
- Patent Title: FinFET with bottom SiGe layer in source/drain
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Application No.: US15043765Application Date: 2016-02-15
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Publication No.: US09911829B2Publication Date: 2018-03-06
- Inventor: Ming-Hua Yu , Pei-Ren Jeng , Tze-Liang Lee
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/78 ; H01L29/06
Abstract:
A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer.
Public/Granted literature
- US20160163836A1 FinFET with Bottom SiGe Layer in Source/Drain Public/Granted day:2016-06-09
Information query
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